Three-dimensional (3D) wafer-to-wafer, die-to-wafer or die-to-die vertical stack technology seeks to achieve the long-awaited goal of vertically stacking many layers of active IC devices such as processors, programmable devices and memory devices to shorten average wire lengths, thereby reducing interconnect RC delay and increasing system performance. One major challenge of 3D interconnects on a single wafer or in a die-to-wafer vertical stack is through-silicon via (TSV) that provides a signal path for high impedance signals to traverse from one side of the wafer to the other. Through-silicon via (TSV) is typically fabricated to provide the through-silicon via filled with a conducting material that passes completely through the layer to contact and connect with the other TSVs and conductors of the bonded layers. In general, Copper has become the metals of choice for the metallization of TSVs because copper has a lower electrical resistivity than most commonly used metals and a higher current carrying capacity. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state. Previous attempts at filling the TSV with a high aspect ratio greater than 3:1, however, often produce TSVs with defects such as a void or a seam created within the conductive plug. The void or seam may cause a series of problems during the fabrication of electronic devices. Reliably producing the TSV is one of the key technologies for the three-dimensional stacking technology. As such, there is a great amount of ongoing effort being directed to the formation of void-free features.